1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device that performs a refresh operation.
2. Description of the Related Art
In general, semiconductor memory devices, such as double data rate synchronous dynamic random access memory (DDR SDRAM), include a plurality of memory banks for storing data. Each of the memory banks includes a plurality of memory cells. The memory cells generally include a cell capacitor for storing an electric charge (corresponding to data) and a cell transistor that serves as a switch. Data stored in the capacitor of the memory cell is determined according to the amount of charge stored. When the charge is large, the memory cell is said to store high data (logic 1). On the other hand, when the charge is small, or the capacitor is discharged, the memory cell is said to store low data (logic 0). That is, a semiconductor memory device stores data by charging and discharging the cell capacitors of the memory cells.
In principle, the charge of cell capacitor should be held constant in the absence of outside activity. However, in actuality, the charge is influenced due to conditions surrounding the cell capacitor, for example, voltage differences between the cell region and a peripheral circuit. In other words, charges may leak out of a charged cell capacitor, or charges may enter a discharged cell capacitor. Changes in the amount of charge being held in the cell capacitor may lead data stored therein being changed, which means that data may be lost. To prevent data from being lost, semiconductor memory devices perform refresh operations. Since refresh operations are widely known to those skilled in the art to which this present invention pertains, a detailed description of refresh operations will not be provided.
As semiconductor fabrication technology continues to make progress, day by day, the integration degree of semiconductor memory devices continues to increase, enabling the dimensions of the memory banks within to be shrunk. Such shrinkage, however, has brought about new concerns. To be specific, the shrinkage in the dimensions of memory banks results in the space between the memory cells becoming increasingly narrow, and this means that when a memory cell operates, other memory cells disposed adjacent to the operating memory cell is likely to be affected, unintentionally. This increased possibility that neighboring memory cells will be affected causes concern.
FIG. 1 is a diagram illustrating a memory bank of a conventional semiconductor memory device. The memory bank of a conventional semiconductor memory device includes a plurality of memory cells, and each of the memory cells includes a cell transistor and a cell capacitor. Each of the memory cells is coupled with a word line and a bit line. Hereafter, for the sake of convenience, three word lines disposed adjacent to each other are representatively described.
Referring to FIG. 1, the memory bank includes first to third word lines WL_K−1, WL_K and WL_K+1, and the word lines are coupled with first to third memory cells MC_K−1, MC_K and MC_K+1, respectively.
Hereafter, it is assumed that the second word line WL_K is activated during an active operation, for the sake of convenience.
When the second word line WL_K is activated, the data stored in the second memory cell MC_K is transmitted to a bit line BL, and the data transmitted to the bit line BL is transmitted to a bit line sense amplifying circuit (not illustrated). The bit line sense amplifying circuit then compares a voltage level of the bit line BL and a voltage level of a complementary bit line /BL with each other and amplifies the voltage difference. As a result, the bit line BL and the complementary bit line /BL are amplified to a pull-up voltage and a pull-down voltage based on the sensed data of the second memory cell MC_K.
Meanwhile, the cell transistor of the second memory cell MC_K and the cell transistor of the third memory cell MC_K+1 are formed in the same well. Therefore, when the second word line WL_K is activated, a threshold voltage of the cell transistor of the third memory cell MC_K+1 coupled with the third word line WL_K+1 is lowered. The decrease in the threshold voltage of the cell transistor of the third memory cell MC_K+1 causes current leakage between the cell transistor of the third memory cell MC_K+1 and the bit line BL. For this reason, if the second word line WL_K continues to be activated, the amount of charge stored in the cell transistor of the third memory cell MC_K+1 is decreased, in other words, the cell transistor of the third memory cell MC_K+1 is discharged, and the data stored in the third memory cell MC_K+1 is eventually lost. When the second memory cell MC_K and the first memory cell MC_K−1 are formed in the same well, current leakage occurs in the first memory cell MC_K−1. Herein, the disposition of the memory cells and wells may be changed depending on design.
On the other hand, a semiconductor memory device having the above-described structure performs a refresh operation in which the first to third word lines WL_K−1, WL_K and WL_K+1 are sequentially activated at a predetermined cycle. In consideration of the refresh operation, the drawback of the current leakage occurring in the third memory cell MC_K+1 may be resolved by controlling the cycling of the refresh operations. In other words, the data may be prevented from being lost if the refresh operation cycle for all word lines is short enough so that the data is not lost due to current leakage. However, it may be inefficient in terms of circuit operation and power consumption to make the other word lines, that is, the first word line WL_K−1 and the second word line WL_K, perform the refresh operations at shorter intervals due to the current leakage occurring in the third memory cell MC_K+1 corresponding to the third word line WL_K+1. In sum, it may not be efficient to make the refresh operation cycles of other word lines shorter for the sake of a specific word line.